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Features ? Configuration device family for configuring Stratix® series, Cyclone® series, APEXTM II, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), MercuryTM, ACEX® 1K, and FLEX® (FLEX 10KE, and FLEX 10KA) devices ? Easy-to-use 4-pin interface to Altera® FPGAs ? Low current during configuration and near-zero standby current ? 5.0-V and 3.3-V operation ? Software design support with the Altera Quartus® II and MAX+PLUS® II development systems for Windows-based PCs as well as Sun SPARCstation, and HP 9000 Series 700/800 ? Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers ? Available in compact plastic packages ? 8-pin plastic dual in-line package (PDIP) ? 20-pin plastic J-lead chip carrier (PLCC) package ? 32-pin plastic thin quad flat pack (TQFP) package ? EPC2 device has reprogrammable Flash configuration memory ? 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface ? Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 ? ISP circuitry is compatible with IEEE Std. 1532 ? Supports programming through Serial Vector Format Files (.svf), Jam Standard Test and Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), and the Quartus II and MAX+PLUS II software via the USB Blaster, MasterBlasterTM, ByteBlasterTM II, EthernetBlaster, or ByteBlasterMVTM download cable ? nINIT_CONF pin allows INIT_CONF JTAG instruction to initiate FPGA configuration ? Can be programmed with Programmer Object Files (.pof) for EPC1 and EPC1441 devices ? Available in 20-pin PLCC and 32-pin TQFP packages
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